1. Technical Field
Embodiments of the present disclosure generally relate to semiconductor integrated circuits and, more particularly, to internal address generation circuits.
2. Related Art
Semiconductor devices, for example, dynamic random access memory (DRAM) devices may have row address paths, column address paths and data paths. The row address path may be created during an operation for selecting one of the word lines using a row address signal supplied from an external device and for amplifying the data stored in at least one memory cell connected to the selected word line using at least one sense amplifier, and the column address path may be created during an operation for selecting one of a plurality of output enable signals using a column address signal supplied from the external device. Further, the data path may be created during an operation for transmitting data on bit lines to an external device through input/output (I/O) lines, the sense amplifiers and data output buffers.
The row address path may be created by a plurality of internal row address signals, one of which is selectively enabled by decoding the row address signal to select one of the word lines, and the column address path may be created by a plurality of internal column address signals, one of which is selectively enabled by decoding the column address signal to select one of the output enable signals.
The semiconductor device may execute an operation for creating the row address path including an active operation and a refresh operation and an operation for creating the column address path including a read operation and a write operation. The semiconductor device may include an internal address generation circuit for generating internal address signals to execute the operations for creating the row address path and the column address path. The internal address signals generated from the internal address generation circuit may include an internal row address signal and an internal column address signal.